📝 Publications

[IEICE TE’21] Low-Power Fast Partial Firmware Update Technique of On-Chip Flash Memory for Reliable Embedded IoT Microcontroller
Jisu Kwon, Moon Gi Seok, and Daejin Park

• Low-power, fast partial firmware update using function maps for efficient on-chip flash memory management.

• Function map enables efficient updates by modifying block addresses without rewriting whole memory.

• Reduces update time, energy use, and memory overhead in IoT microcontrollers.

[IEEE COOLChips’20] User Insensible Sliding Firmware Update Technique for Flash-Area/Time-Cost Reduction toward Low-Power Embedded Software Replacement
Jisu Kwon, Moon Gi Seok, and Daejin Park

Slides | Video

• User insensible sliding firmware update reduces flash memory usage and device pause time by updating only function blocks instead of entire firmware.

• Achieves 63.64% memory overhead reduction, 79.98% pause time reduction, and 78.78% energy consumption reduction.

[VLSI-TSA’25] Sliding-Window-based Fast and Lightweight ADC Pseudo-Randomness Compensation Technique for Low-Cost ADC
Jisu Kwon, and Daejin Park Slides | Poster

• Sliding-window-based ADC compensation reduces noise using neural networks.

• Minimizes hardware usage, enhances ADC performance with software compensation.

• Achieves 1.61× ENOB improvement, 5.82× processing time reduction under 20 dB noise.

[IEEE MWSCAS’23] Hardware Accelerator Processing Element Unit Dynamic Pruning using Runtime RTL Simulation Reconfiguration
Jisu Kwon, Heuijee Yun, and Daejin Park

Poster

• Dynamic MAC unit pruning reduces neural accelerator area and power consumption by removing inactive processing elements.

• Empirical RTL simulation analyzes signal switching to optimize pruning while maintaining accuracy.

• Achieves up to 9.78% signal switching reduction, 4.25% area savings, and only 1% accuracy loss.

[Applied Sciences’25] MAIL: Micro-Accelerator-in-the-Loop Framework for MCU Integrated Accelerator Peripheral Fast Prototyping
Jisu Kwon, and Daejin Park

• Micro-Accelerator-in-the-Loop (MAIL) framework enables fast prototyping of MCU-integrated accelerators for TinyML.
• Combines software emulation and cycle-accurate RTL simulation to evaluate hardware-software interaction.
• Supports parameter exploration for optimizing accelerator performance and resource usage.
• Reduces latency and improves efficiency in TinyML applications.

[ACM/IEEE EMSOFT’23] Work-in-Progress: Micro-Accelerator-in-the-Loop Framework for MCU Integrated Accelerator Peripheral Fast Prototyping
Jisu Kwon, and Daejin Park

(BK21+ CS SCI Conference) | Slides | Poster

• Micro-Accelerator-in-the-Loop (MAIL) framework enables fast prototyping of MCU-integrated accelerators.

• Combines system emulation and cycle-accurate RTL simulation for efficient performance profiling.

• Achieves up to 84.32% and 61.32% cycle latency reduction in TinyML applications.

[IEEE ISCAS’21] Metamorphic Edge Processor Simulation Framework Using Flexible Runtime Partial Replacement of Software-Embedded Verilog RTL Models,
Jisu Kwon, Sejong Oh, and Daejin Park

Slides | Video

• Metamorphic edge processor simulation framework accelerates RTL verification by replacing redundant models with software emulation.

• Virtual layer enables dynamic partial RTL model replacement at runtime.

• Achieves significant simulation speedup while maintaining parameter exploration flexibility.

[IEEE ESL’23] Efficient Partial Weight Update Techniques for Lightweight On-Device Learning on Tiny Flash-Embedded MCUs
Jisu Kwon, and Daejin Park

Slides | Poster | Video

• Partial weight update technique reduces memory usage in on-device learning by updating only selected weights stored in flash.

• Gradient-based selection minimizes accuracy loss while optimizing SRAM usage.

• Achieves 76.1% accuracy with only 18.52% weight updates, reducing APDP by up to 46.9%.

[HPC-Asia’21] Toward Data-Adaptable TinyML Using Model Partial Replacement for Resource Frugal Edge Device
Jisu Kwon, and Daejin Park

Poster | Video

• Model partial replacement enables data-adaptable TinyML by updating only specific network components in resource-limited edge devices.

• Reduces model size, maintains accuracy, and optimizes flash memory usage.

• Enhances inference efficiency without full firmware updates.