📝 Publications
1️⃣ Efficient Firmware
[IEICE TE’21] Low-Power Fast Partial Firmware Update Technique of On-Chip
Flash Memory for Reliable Embedded IoT Microcontroller
Jisu Kwon, Moon Gi Seok, and Daejin Park
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Low-power, fast partial firmware update using function maps for efficient on-chip flash memory management.
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Function map enables efficient updates by modifying block addresses without rewriting whole memory.
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Reduces update time, energy use, and memory overhead in IoT microcontrollers.
[IEEE COOLChips’20] User Insensible Sliding Firmware Update Technique for
Flash-Area/Time-Cost Reduction toward Low-Power Embedded Software Replacement
Jisu Kwon, Moon Gi Seok, and Daejin Park
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User insensible sliding firmware update reduces flash memory usage and device pause time by updating only function blocks instead of entire firmware.
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Achieves 63.64% memory overhead reduction, 79.98% pause time reduction, and 78.78% energy consumption reduction.
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Sensors’23Optimized Replication of ADC-Based Particle Counting Algorithm with Reconfigurable Multi-Variables in Pseudo-Supervised Digital Twining of Reference Dust Sensor Systems, Seungmin Lee, Jisu Kwon, and Daejin Park. -
IEEE Access’23Runtime Tracking-Based Replication of On-Chip Embedded Software Using Transfer Function Learning for Dust Particle Sensing Systems, Seungmin Lee, Jisu Kwon, and Daejin Park. IEEE Access’22Efficient Sensor Processing Technique Using Kalman Filter-Based Velocity Prediction in Large-Scale Vehicle IoT Application, Jisu Kwon, and Daejin Park.IEEE ICAIIC’22Implementation of Computation-Efficient Sensor Network for Kalman Filter-based Intelligent Position-Aware Application, Jisu Kwon, and Daejin Park.IEEE ICCE-Asia’20Segmented Polynomial Approximation for Controlled System Characteristic Estimation on Lightweight Edge Device, Minsung Kim, Jongheon Baek, Jiwoong Jung, Jisu Kwon, and Daejin Park.IEEE ISPACS’19Function Block-Based Robust Firmware Update Technique for Additional Flash-Area/Energy-Consumption Overhead Reduction, Jisu Kwon, Jeonghun Cho, and Daejin Park.IEEE COOLChips’19Efficient Flash Memory Access Power Reduction Techniques for IoT-Driven Rare-Event Logging Application, Jisu Kwon, Jeonghun Cho, and Daejin Park. (Poster Session)
2️⃣ Efficient Hardware
[VLSI-TSA’25] Sliding-Window-based Fast and Lightweight ADC Pseudo-Randomness
Compensation Technique for Low-Cost ADC
Jisu Kwon, and Daejin Park
Slides
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Poster
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Sliding-window-based ADC compensation reduces noise using neural networks.
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Minimizes hardware usage, enhances ADC performance with software compensation.
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Achieves 1.61× ENOB improvement, 5.82× processing time reduction under 20 dB noise.
[IEEE MWSCAS’23] Hardware Accelerator Processing Element Unit Dynamic Pruning using
Runtime RTL Simulation Reconfiguration
Jisu Kwon, Heuijee Yun, and Daejin Park
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Dynamic MAC unit pruning reduces neural accelerator area and power consumption by removing inactive processing elements.
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Empirical RTL simulation analyzes signal switching to optimize pruning while maintaining accuracy.
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Achieves up to 9.78% signal switching reduction, 4.25% area savings, and only 1% accuracy loss.
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Applied Sciences’22Hardware/Software Co-Design for TinyML Voice-Recognition Application on Resource Frugal Edge Devices, Jisu Kwon, and Daejin Park. -
ISOCC’22Lightweighted AI-based Inference using Deterministic Randomness Compensation for Microcontroller ADC Resolution Enhancement, Jisu Kwon, and Daejin Park. -
JIPS’20GPU-Based ECC Decode Unit for Efficient Massive Data Reception Acceleration, Jisu Kwon, Moon Gi Seok, and Daejin Park.
3️⃣ SoC Verification
[Applied Sciences’25] MAIL: Micro-Accelerator-in-the-Loop Framework for MCU Integrated
Accelerator Peripheral Fast Prototyping
Jisu Kwon, and Daejin Park
- Micro-Accelerator-in-the-Loop (MAIL) framework enables fast prototyping of MCU-integrated accelerators for TinyML.
- Combines software emulation and cycle-accurate RTL simulation to evaluate hardware-software interaction.
- Supports parameter exploration for optimizing accelerator performance and resource usage.
- Reduces latency and improves efficiency in TinyML applications.
[ACM/IEEE EMSOFT’23] Work-in-Progress: Micro-Accelerator-in-the-Loop Framework for MCU
Integrated Accelerator Peripheral Fast Prototyping
Jisu Kwon, and Daejin Park
(BK21+ CS SCI Conference) | Slides | Poster
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Micro-Accelerator-in-the-Loop (MAIL) framework enables fast prototyping of MCU-integrated accelerators.
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Combines system emulation and cycle-accurate RTL simulation for efficient performance profiling.
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Achieves up to 84.32% and 61.32% cycle latency reduction in TinyML applications.
[IEEE ISCAS’21] Metamorphic Edge Processor Simulation Framework Using Flexible
Runtime Partial Replacement of Software-Embedded Verilog RTL Models,
Jisu Kwon, Sejong Oh, and Daejin Park
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Metamorphic edge processor simulation framework accelerates RTL verification by replacing redundant models with software emulation.
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Virtual layer enables dynamic partial RTL model replacement at runtime.
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Achieves significant simulation speedup while maintaining parameter exploration flexibility.
IEEE ICAIIC’25A Dynamic Linking Framework for Efficient QEMU Peripheral Development and Maintenance, Gihyeon Jeon, Jisu Kwon, and Daejin Park.
4️⃣ TinyML
[IEEE ESL’23] Efficient Partial Weight Update Techniques for Lightweight On-Device Learning
on Tiny Flash-Embedded MCUs
Jisu Kwon, and Daejin Park
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Partial weight update technique reduces memory usage in on-device learning by updating only selected weights stored in flash.
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Gradient-based selection minimizes accuracy loss while optimizing SRAM usage.
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Achieves 76.1% accuracy with only 18.52% weight updates, reducing APDP by up to 46.9%.
[HPC-Asia’21] Toward Data-Adaptable TinyML Using Model Partial Replacement for Resource
Frugal Edge Device
Jisu Kwon, and Daejin Park
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Model partial replacement enables data-adaptable TinyML by updating only specific network components in resource-limited edge devices.
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Reduces model size, maintains accuracy, and optimizes flash memory usage.
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Enhances inference efficiency without full firmware updates.
IEEE ISPACS’22Neural Network-based Approximate Quality Prediction for Parameter Exploration in Industrial Manufacturing, Jisu Kwon, Moon Gi Seok, and Daejin Park.
️5️⃣️ Others
ACM TMCS’25Hyperparameter Tuning with Gaussian Processes for Optimal Abstraction Control in Simulation-based Optimization of Smart Semiconductor Manufacturing Systems, Moon Gi Seok, Wen Jun Tan, Wentong Cai, Jisu Kwon, and Seon Han Choi.
6️⃣ Domestic Journal Articles
IEMEK JESA’22Collaborative Streamlined On-Chip Software Architecture on Heterogenous Multi-Cores for Low-Power Reactive Control in Automotive Embedded Processors, Jisu Kwon, and Daejin Park.-
JKIICE’21Low-Power Metamorphic MCU using Partial Firmware Update Method for Irregular Target Systems Control, Jongheon Baek, Jiwoong Jung, Minsung Kim, Jisu Kwon, and Daejin Park. -
JKIICE’20Acceleration of ECC Computation for Robust Massive Data Reception under GPU-based Embedded Systems, Jisu Kwon, and Daejin Park. -
JKIICE’20Velocity and Distance Estimation-based Sensing Data Collection Interval Control Technique for Vehicle Data-Processing Overhead Reduction, Jisu Kwon, and Daejin Park. IEMEK JESA’19Efficient Flash Memory Access Power Reduction Techniques for IoT-Driven Rare-Event Logging Application, Jisu Kwon, and Daejin Park.
7️⃣ Books and Chapters
Low-Power Digital System Design - Practical Approach, TNES, 2021.
Daejin Park, and Jisu Kwon
- This book covers low-power system-on-chip design methodologies and implementation techniques, from gate-level to architectural approach and software-hardware interfaces:
- Toggle minimization in CMOS, gate, RTL, architecture, and software level.
- Clock gating, data filtering-based toggle propagation minimization
- Edge-triggered event-driven approach to reduce the active circuits
- Multi-clock domain and asynchronous circuit design techniques using buffers.
- Synchronizer between clock-crossing regions
- Power-gating and architectural circuit design method