I am a post-doctoral researcher at the Korea Advanced Institute of Science and Technology (KAIST), working in the VLSI Laboratory under the supervision of Prof. Bongjin Kim.

I received my Ph.D. in Electronic and Electrical Engineering from Kyungpook National University in August 2025, advised by Prof. Daejin Park . I also earned my bachelor’s degree in Electronics Engineering from the same university in August 2019 (early graduation).

My research mainly focuses on SW/HW full-stack with contributions in:

• SW FW Efficient embedded software: I have worked extensively on tackling challenges for on-chip flash firmware update, such as robustness, and efficiency. My work includes achieving efficient accelerator control firmware.
• HW Efficient hardware design: I work to comprehensively mitigate hardware overhead, including Arm compatible CNN accelerators, ADC error compensation with MLP, and customized PCIe accelerator controllers. Some of my recent work, including MPW chips, is currently under review.
• HW SW Efficient SoC verification platform: My work includes an emulator-simulator mixed framework to speed up partial RTL verification within SoCs, which is driven by embedded software.
• HW Automotive IP RTL Design: My work includes communication interface module RTL design and AMBA bus integration for automotive sensor ASICs, such as DSI3, SENT, I2S.

My research aims to achieve efficient AI accelerator design and utilize by tightly-coupling all full-stack layers of HW, SW, and FW. My 20+ published papers will be the basis of my research goal.

I was selected as the first integrated B.S./M.S./Ph.D. student at university and was awarded a Ph.D. Research Fellowship from the National Research Foundation (NRF) of Korea.